1. Field of the Invention
The present invention relates to a flat panel display apparatus and, more particularly, to a data interfacing apparatus for interfacing between a frame memory and an address electrode driving means for driving address electrodes of a flat panel display system which uses a red-green-blue(RGB) strip-type plasma display panel.
2. Description of the Prior Art
Customers of television sets have demanded slim display apparatus which have wide screen. Since existing cathode ray tube (CRT) equipments have started reveal limitations in fulfilling such a demand, they are replaced by a so-called flat panel display (FPD) apparatuses that has a wide and slim display area. Further, many research projects in FPD field are globally in process.
The FPD apparatus is largely divided into an emissive device and a non-emissive device. The emissive device, usually called an active emitting device, is a device which emits a light by itself. Typical examples of the emissive devices are a field emission display (FED) device, a vacuum fluorescent display (VFD) type device, an electro-luminescence (EL) type device, a plasma display panel (PDP) and the like. The non-emissive device is called a passive light emitting device, and there are examples of the non-emissive device such as a liquid crystal display (LCD) device, an electro-chromic display (ECD), an electro-phoretic display (EPID) and the like.
Currently, the LCD device occupies a main stream of production in electric and electronis goods such as desk clocks, calculators, lap-top computers and the like. Although this device can be adopted to television sets having a screen size of more than 21 inches, it has also shown the limitations in manufacturing process of panels and in obtaining satisfiable products. Further, it has problems of having a narrow visual field angle and a response rate varies subject to a temperature change. Due to a capability of solving these problems of the LCD device, the PDP newly attracts public attention as a next generation FPD.
Since, in principle, the PDP emits a light by itself similarly to that of a fluorescent lamp, it has uniform brightness and a high contrast although a screen area of the PDP is as wide as a screen area of the CRT. In addition, the PDP has a visual field angle of more than 140 degrees and above, and is well-known as the best and widest screen display device which has a screen size of 21 to 55 inches. The panel manufacturing process of the PDP is simplified as compared with that of the LCD device and thereby saves a manufacturing cost. However, because the manufacturing cost of the PDP is more expensive than that of the CRT, manufacturers have sought to reduce the manufacturing cost.
The plasma display is largely classified as a direct current (DC) type and an alternating current (AC) type according to a structural difference of a discharge cell thereof and a form of a driving voltage based on the structural difference. The DC type is driven by a DC voltage whereas the AC type is driven by a sinusoidal AC voltage or by a pulse voltage. The AC type includes such a structure that a dielectric layer covers an electrode to be served as a current regulation resistor. On the other hand, the DC type includes such a structure that an electrode is exposed to a discharge room as it is and a discharge current comes to flow during a supply of the discharge voltage. Because the AC type has the electrode which is covered with the dielectric, it is more durable than the DC type. The AC type has a further advantage in that a wall electric charge which is generated on a surface of the dielectric as a result of a polarization causes the cell to have a memory function therein, and is more applicable than others in the field of display devices.
A color PDP includes a structure of three terminals wherein a special electrode is installed in order to improve discharge characteristics thereof. Namely, the 3-terminal structure comprises three electrodes per unit cell for a display which are an address electrode for entering data, a maintenance electrode for sequentially scanning a line and for maintaining a cell discharge, and a bus electrode for helping a discharge maintenance.
A number of the address electrode for entering data is determined in accordance with a horizontal resolution. For example, in a case where samples of the red, green and blue colors per line are 853, a total number of the samples amounts to 2559. Therefore, a required number of the address electrodes is also 2559. In a case where an arrangement of the address electrode has a strip form, red, green and blue electrodes are arranged repeatedly.
As described above, because a circuit arrangement of an electrode driving section is restricted to a consideration of a space utilization when thousands of the address electrodes are arranged on one side, an upper and lower electrode driving system is adapted wherein section for driving 1280 electrodes, which are ordered in an odd-numbered sequence, are arranged at an upper end portion of a panel whereas section for driving 1279 electrodes, which are ordered in an even-numbered sequence, are arranged at a lower end portion thereof (refer to U.S. Pat. No. 4,695,838).
Meanwhile, in order to display a TV signal of a system of national television system committee (NTSC) on the PDP, a data processing section converts an interlaced scanning system into a sequential scanning system, and also converts data into data of a subfield system for a PDP contrast-processing. Further, the data processing section provides 1280 RGB pixel data per line to the electrode driving section for driving the upper and lower address electrodes of the panel of the PDP in harmony with the arrangement of the address electrode.
Conventionally, a video data processing section of the PDP includes a data rearranging section for rearranging digital RGB sample data into subfield data for the contrast-processing, a frame memory section for converting one scanning system into the other, a data interfacing section, and a timing control section.
A composite video signal received through an antenna is processed into an analog signal by a video/audio signal processing section, and the analog signal is converted into a digital video signal by an analog-to-digital converting section. This digital video signal is transferred in turn through the data rearranging section, the frame memory section and the data interfacing section to an address electrode driving section of a data stream type which is suitable for contrast-processing of the PDP. For suitable timing-controls to respective sections, the timing controlling section generates timing control signals for respective sections by frequency-dividing a main clock signal.
The data interfacing section has roles of storing a horizontal line data sequentially outputted from the frame memory section and outputting the horizontal line data suitable for input order of the address electrode driving section. The data interfacing section needs a storing capacity of at least 5118 bits in order to simultaneously input and output the horizontal line data that amount to 2559 bits (853 bits.times.3) in a color PDP-TV whose one horizontal line consists of 853 pixels. Generally, the data interfacing section has two data interfacing chips in the PDP-TV with dual address electrodes, each of upper and lower data interfacing chips needs of a storing capacity at least 2559 bits.
There has been a prior PDP-TV system using a delayed flip-flop as a storing logic of the data interfacing chip. In the prior PDP-TV system, the data interfacing chip has to includes 2592 delayed flip-flops, which are usually designed as a matrix structure of 48 rows by 54 columns, to store the horizontal line data (2559 bits). Since 48 (bits).times.54 (times) output data from the frame memory section have to be separately transferred to respective 2592 delayed flip-flops, a pattern of connection paths between the frame memory section and the respective 2592 delayed flip-flops becomes very complex. It is hard to design a data interfacing chip which has such a logic. Furthermore, many control signals are necessary for controlling the 2592 delayed flip-flops and such a data interfacing chip is not flexible for increasing a storing capacity.
On the other hand, the data interfacing chip includes two provisional storing logics and each provisional storing logic consists of 2559 delayed flip-flops. This configuration of the data interfacing chip purposes for a continuity of a data flow in input and output operations by simultaneously performing receipt of a current horizontal line data from the frame memory and outputting the previously received horizontal line data. A logic for selecting one between the two provisional storing logics to store the data transferred from the frame memory is necessary, and a demultiplexer has been used for the logic. For example, when an amount of output data transferred every time from the frame memory is 48 bits, an input pin number of the demultiplexer should be 48 and every output pin of the demultiplexer should be connected to 5184 delayed flip-flops which consist of the two provisional storing logics. Besides, an additional logic for controlling input and output operations of the demultiplexer is necessary. Accordingly, connection paths between the frame memory and the two provisional storing logics of the data interfacing chip become very complicated and it is hard to design the data interfacing chip with such complicated connection paths.